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signal and power isolated can transceiver with integrated isolat ed dc - to - dc converter adm3053 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.co m fax: 781.461.3113 ? 2011 analog devices, inc. all rights reserved. f eatures 2.5 kv rms s ignal and power i solated can transceiver iso power integrated isolated dc - to - dc converter 5 v operation on v cc 5 v or 3.3 v operation on v io complies with iso 11898 s tandard high s peed d ata r ates of up to 1 mbps unpowered n odes do not d isturb the bus connect 110 or more nodes on the bus slope c ontrol for reduced emi thermal shutdown protection high common - mode transient immunity: >25 kv/s safety and regulatory approvals ( pending ) ul recognition 2500 v rms for 1 minute per ul 1577 vde certificate of conformity din en 60747 - 5 - 2 (vde 0884 rev.2 ): 2003 - 01 industrial o perating temperature range (?40c to +85c) available in w ide - body, 20 - lead soic package applications can d ata b uses industrial f ield n etworks general description the adm30 53 is an isolated controller area network (can) physical layer transceiver with an integrated isolated dc - to - dc converter. the adm3053 complies with the iso 11898 standard . the device employs analog devices, inc., i coupler? technology to combine a 2 - chann el isolator, a can transceiver, and analog devices iso power? dc - to - dc converter into a single soic surface mount package. an on - chip oscillator outputs a pair of square waveforms that drive an internal transformer to provide isolated power . the device is p owered by a single 5 v supply realizing a fully isolated can solution. the adm3053 creates a fully isolated interface between the can protocol controller and the physical layer bus. it is capable of running at data rates of up to 1 mbps. the device has c urrent limiting and thermal shutdown features to protect against output short circuits. the part is fully s pecified over the industrial temperature range and is available in a 20- lead, wide - body soic package. the adm3053 contains isopower technology that uses high frequency switching elements to transfer power through the transformer. special care must be taken during printed circuit board (pcb) layout to meet emissions standards. refer to the an - 0971 applicat ion note , control of radiated emissions with iso power devices, for details on board layout considerations . functional block dia gram adm3053 t xd v c c rxd isolation barrier gnd1 gnd2 logic side bus side enc ode de c ode de c ode enc ode oscil l a t or re c tifier regul a t or v isoout di g ital isol a tion ic oupler iso p ower dc-to-dc c on v er t er v io v isoin r s canh canl v ref reference voltage receiver can transceiver txd r s rxd v ref gnd2 v cc slope/ standby driver protection 09293-001 figure 1 .
adm3053 rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 4 switching characteristics ............................................................ 4 regulatory information ............................................................... 5 insulation an d safety - related specifications ............................ 5 vde 0884 insulation characteristics (pending) ...................... 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance cha racteristics ............................................. 9 test circuits ..................................................................................... 12 circuit description ......................................................................... 13 can trans ceiver operation ..................................................... 13 signal isolation ........................................................................... 13 power isolation ........................................................................... 13 tr uth tables ................................................................................. 13 thermal shutdown .................................................................... 1 3 dc correctness and magnetic field immunity ........................... 13 applications information .............................................................. 15 pcb layout ................................................................................. 15 emi considerations ................................................................... 15 insulation lifetime ..................................................................... 15 typical applications ....................................................................... 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 18 revision history 5/11 revision 0: initial version
adm3053 rev. 0 | page 3 of 20 specifications all voltages are relative to their respective ground; 4.5 v v cc 5.5 v ; 3.0 v v io 5.5 v . all m inimum/maximum speci fications apply over the entire recommended operation range, unless otherwise noted. all typical specifications are at t a = 25c, v cc = 5 v , v io = 5 v unless otherwise noted. table 1. parameter symbol min typ max unit test condition s supply current logic side iso power current recessive state i cc 29 36 ma r l = 60 ?, r s = l ow, s ee figure 25 dominant state i cc 195 232 ma r l = 60 ?, r s = l ow, s ee figure 25 txd/rxd data rate 1 mbps i cc 139 170 ma r l = 60 ?, r s = l ow, s ee figure 25 logic s ide i coupler current txd/rxd data rate 1 mbps i io 1.6 2.5 ma driver logic inputs input voltage high v ih 0.7 v io v output recessive input voltage low v il 0.25 v io v output dominan t cmos logic input currents i ih , i il 500 a txd differential outputs recessive bus voltage v canl , v canh 2.0 3.0 v txd = h igh , r l = , s ee figure 22 canh output voltage v canh 2.75 4.5 v txd = l ow , s ee figure 22 canl output voltage v canl 0.5 2.0 v txd = l ow , s ee figure 22 differential output voltage v od 1.5 3.0 v txd = l ow , r l = 45 ? , s ee figure 22 v od ? 500 +50 mv txd = h igh , r l = , s ee figure 22 short - circuit current , canh i sccanh ? 200 ma v canh = ?5 v ? 100 ma v canh = ? 36 v short - circuit current, canl i sccanl 200 ma v canl = 36 v receiver differential inputs differential input voltage recessive v idr ? 1.0 +0.5 v ? 7 v < v canl , v canh < + 12 v, s ee figure 23, c l = 15 pf differential input voltage dominant v idd 0.9 5.0 v ? 7 v < v canl , v canh < + 12 v, s ee figure 23, c l = 15 p f input voltage hysteresis v hys 150 mv see figure 3 canh, canl input resistance r in 5 25 k? differential input resistance r diff 20 100 k? logic outputs output low voltage v ol 0.2 0.4 v i out = 1.5 ma output high voltage v oh v io ? 0.3 v io ? 0.2 v i out = ?1.5 ma short circuit current i os 7 85 ma v out = gnd1 or v io voltage reference reference output voltage v ref 2.025 3.025 v |i ref = 50 a| common - mode transient immunity 1 25 kv/s v cm = 1 kv, transient magnitude = 800 v slop e control current for slope control mode i slope ? 10 ? 200 a slope control mode voltage v slope 1.8 3.3 v 1 cm is the maximum common - mode voltage slew rate that can be sustained while maintaining specification - compliant operation. vcm is the common - mode potential difference between the logic and bus sides. the transient magnitude is the range over which the common mode is slewed. the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges.
adm3053 rev. 0 | page 4 of 20 timing specification s all voltages are relative to their respective ground; 3.0 v v io 5.5 v; 4.5 v v cc 5.5 v. t a = ? 40c to + 85 c, unless otherwise noted. table 2. parameter symbol min typ max unit test conditions driver maximum data rate 1 mbps propagation delay from txd on to bus active t ontxd 90 ns r s = 0 ?; see figure 2 and figure 24 r l = 60 ?, c l = 100 pf propagation delay from txd off to bus inactive t offtxd 120 ns r s = 0 ? ; see figure 2 and figure 24 r l = 60 ?, c l = 100 pf receiver propagation delay from txd on to receiver active t onrxd 200 ns r s = 0 ?; see figure 2 630 ns r s = 47 k?; see figure 2 propagation delay from txd off to receiver inactive 1 t offrxd 250 ns r s = 0 ?; see figure 2 480 ns r s = 47 k?; see figure 2 canh, canl sl ew rate |sr| 7 v/s r s = 47 k? 1 guaranteed by design and characterization . switching characteri stics 0.25v io 0.9v v or v od 0v 0v v io 0.5v 0.4v v diff v rxd v io v txd v io ? 0.3v 0.7v io v diff = v canh ? v canl t ontxd t offtxd t onrxd t offrxd 09293-002 figure 2 . driver propagation delay, rise/fall timing
adm3053 rev. 0 | page 5 of 20 0.5 0.9 v rxd high low v hys v id (v) 09293-004 figure 3 . receiver i nput hysteresis regulatory informati on table 3 . pending adm3053 approvals organization approval type notes ul to be recognized under the component recognition program of underwriters laboratories, inc. in accordance with ul 1577, each adm3053 is proof tested by applying an insulation test volt age 2500 v rms for 1 second. vde to be certified according to din en 60747 -5-2 (vde 0884 rev. 2): 2003 -01 in accordance with vde 0884 -2. insulation and safet y - related specificatio ns table 4. parameter symbol value unit condition s rated dielectric insulation voltage 2500 v rms 1- minute duration minimum external air gap (clearance) l(i01) 7.7 mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 7.6 mm me asured from input terminals to output terminals, shortest distance along body minimum internal gap (internal clearance) 0.017 min mm insulation distance through insulation tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 -1 isolation group iiia material g roup ( din vde 0110: 1989 -01, table 1 )
adm3053 rev. 0 | page 6 of 20 vde 0884 insulation characteristics (pen ding) this isolator is suitable for basic electrical isolation only within the safety limit data. maintenance of the safety data mu st be ens ured by means of protective circuits. table 5. description conditions symbol characteristic unit classifications installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv 300 v rms i to iii 400 v rms i to ii climatic classification 40/85/21 pollution degree din vde 0110, see table 3 2 voltage maximum working insulation voltage v iorm 424 v peak input -to - output test voltage v pr method b1 v iorm 1.875 = v pr , 100% production tested, t m = 1 sec, partial discharge < 5 pc 795 v peak highest allowable overvoltage ( transient overvoltage, t tr = 10 sec) v tr 4000 v peak safety - limiting values maximum value allowed in the event of a failure case temperature t s 150 c input current i s, input 265 ma output current i s, output 335 ma insulation resistance at t s v io = 500 v r s >10 9 ?
adm3053 rev. 0 | page 7 of 20 absolute maximum rat ings t a = 25c, unless otherwise noted. all voltages are relative to their respective ground. table 6. parameter rating v cc ? 0.5 v to + 6 v v io ? 0.5 v to +6 v digital input voltage , txd ? 0.5 v to v io + 0.5 v digital output voltage , rxd ? 0.5 v to v io + 0.5 v canh, canl ? 36 v to + 36 v v ref ? 0.5 v to +6 v r s ? 0.5 v to +6 v operating temperature range ? 40c to +85c storage temperature range ? 55c to +150c esd (human body model) 3 kv lead tempera ture soldering (10 sec) 300c vapor phase (60 sec) 215c infrared (15 sec) 220c ja thermal impedance 53c /w t j junction temperature 130c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 7. maximum continuous working voltage 1 parameter max unit reference standard ac voltage bipolar waveform 424 v peak 50 year minimum lifetime unipolar waveform basic insulation 560 v peak maximum approved working voltage per vde 0884 part 2 dc voltage basic insulation 560 v peak maximum approved working voltage per vde 0884 part 2 1 refers to continuous voltage magnitude imposed across the isolation barrier. see the insulation lifetime section for more details. esd caution
adm3053 rev. 0 | page 8 of 20 pin configuration an d function descripti ons gnd1 1 nc 2 gnd1 3 rxd 4 gnd2 20 v isoin 19 r s 18 canh 17 txd 5 gnd2 16 v io 6 canl 15 gnd1 7 v ref 14 v cc 8 gnd2 13 gnd1 9 v isoout 12 gnd1 10 gnd2 1 1 adm3053 t op view (not to scale) notes 1. nc = no connect. do not connect to this pin. 2. pin 12 and pin 19 must be connected externally. 09293-005 figure 4 . pin configuration table 8. pin function descriptions pin no. mnemonic description 1 gnd1 ground, logic side. 2 nc no connect. do not connect to this pin. 3 gnd1 ground, logic side. 4 r x d receiver output data. 5 t x d driver input data. 6 v io i coupler power supply. it is recommended that a 0.1 f and a 0. 01 f decoupling capacitor be fitted between pin 6 and gnd1 . see figure 28 for layout recommendations. 7 gnd1 ground, logic side. 8 v cc iso power power supply. it is recommended that a 0.1 f and a 10 f decoupling capacitor be f itted between pin 8 and pin 9. 9 gnd1 ground, logic side. 10 gnd1 ground, logic side. 11 gnd2 ground, bus side. 12 v isoout isolated power supply output. this pin must be connected externally to v isoin . it is recommended that a reservoir capacitor of 1 0 f and a decoupling capacitor of 0.1 f be fitted between pin 12 and pin 11. 13 gnd2 ground (bus side). 14 v ref reference voltage o utput. 15 canl low - level can voltage input / output. 16 gnd2 ground ( bus side). 17 canh high - level can voltage input/ou tput. 18 r s slope resistor input. 19 v isoin isolated power supply input. this pin must be connected externally to v isoout . it is recommended that a 0.1 f and a 0.01 f decoupling capacitor be fitted between pin 19 and pin 20. 20 gnd2 ground ( bus side) .
adm3053 rev. 0 | page 9 of 20 typical performance characteristics 160 0 20 40 60 80 100 120 140 100 1000 supply current, i cc (ma) data rate (kbps) v cc = 4.5v, v io = 5v v cc = 5.5v, v io = 5v v cc = 5v, v io = 5v 09293-100 figure 5 . supply current, i cc vs. data rate 50 45 40 35 30 25 20 15 10 5 0 0 10 20 30 40 50 60 70 80 slew rate (v/s) resistance, r s (?) 09293-101 figure 6 . driver slew rate vs . resistance , r s 5.5 4.5 3.5 2.5 1.5 0.5 100 1000 supply current, i io (ma) data rate (kbps) v io = 3.3v v io = 5v 09293-102 figure 7 . supply current, i io vs. da ta r ate 180 175 170 165 160 155 150 ?40 85 60 35 10 ?15 receiver input hysteresis (mv) temperature (c) v cc = 5v, v io = 5v v cc = 5v, v io = 3.3v 09293-103 figure 8 . receiver i nput h ysteresis vs. temperature 53 52 51 50 49 48 47 ?40 85 60 35 10 ?15 propagation delay txd on to bus active, t ontxd (ns) temperature (c) v cc = 5v, v io = 5v v cc = 5v, v io = 3.3v 09293-104 figure 9 . propagation delay from txd o n to bus active vs . temperature 96 94 92 90 88 86 84 82 80 78 ?40 85 60 35 10 ?15 propagation delay txd off to bus inactive, t offtxd (ns) temperature (c) v cc = 5v, v io = 5v v cc = 5v, v io = 3.3v 09293-105 figure 10 . propagation d elay from txd o ff to b us i nactive vs. temperature
adm3053 rev. 0 | page 10 of 20 152 150 148 146 144 142 140 138 136 134 ?40 85 60 35 10 ?15 propagation delay txd off to bus inactive, t offtxd (ns) temperature (c) v cc = 5v, v io = 5v, r s = 0? v cc = 5v, v io = 3.3v, r s = 0? 09293-106 figure 11 . propagation delay from txd o ff to b us i nactive vs. temperature 600 500 400 300 200 100 0 ?40 85 60 35 10 ?15 propagation delay txd on to receiver active, t onrxd (ns) temperature (c) v cc = 5v, v io = 5v, r s = 47k? v cc = 5v, v io = 3.3v, r s = 47k? 09293-107 figure 12 . propagation d elay from txd o n to r eceiver a ctive vs. temperature 250 200 150 100 50 0 ?40 85 60 35 10 ?15 propagation delay txd off to receiver inactive, t offrxd (ns) temperature (c) v cc = 5v, v io = 5v, r s = 0? v cc = 5v, v io = 3.3v, r s = 0? 09293-108 figure 13 . propagation delay from txd o ff to r eceiver i nactive vs. temperature 330 325 320 315 310 305 300 295 290 285 280 275 ?40 85 60 35 10 ?15 propagation delay txd off to receiver inactive, t offrxd (ns) temperature (c) v cc = 5v, v io = 5v, r s = 47k? v cc = 5v, v io = 3.3v, r s = 47k? 09293-109 figure 14 . propagation delay from txd o ff to r eceiver i nactive vs. temperature 2.55 2.50 2.45 2.40 2.35 2.30 2.25 ?40 85 60 35 10 ?15 differential output voltage dominant, v od (v) temperature (c) v cc = 5v, v io = 5v, r l = 60? v cc = 5v, v io = 3.3v, r l = 60? v cc = 5v, v io = 5v, r l = 45? v cc = 5v, v io = 3.3v, r l = 45? 09293- 1 10 figure 15 . differential output v oltage d ominant vs. temperature 2.55 2.50 2.45 2.40 2.35 2.30 2.25 4.5 5.5 5.3 5.1 4.9 4.7 differential output voltage dominant, v od (v) supply voltage, v cc (v) v io = 5v, t a = 25c, r l = 60? v io = 5v, t a = 25c, r l = 45? 09293- 11 1 figure 16 . differential o utput v oltage d ominant vs. supply v oltage , v cc
adm3053 rev. 0 | page 11 of 20 2.80 2.75 2.70 2.65 2.60 2.55 2.50 2.45 2.40 ?40 85 60 35 10 ?15 reference voltage, v ref (v) temperature (c) v cc = 5v, v io = 5v, i ref = +50a v cc = 5v, v io = 5v, i ref = ?50a v cc = 5v, v io =5v, i ref = +5a v cc = 5v, v io = 5v, i ref = ?5a 09293- 1 12 figure 17 . reference voltage vs . temperature 160 140 120 100 80 60 40 20 0 ?40 85 60 35 10 ?15 supply current, i cc (ma) temperature (c) v cc = 5v v io = 5v data rate = 1mbps r l = 60? 09293- 1 13 figure 18 . s upply current i cc vs. temperature 140 138 136 134 132 130 128 126 124 122 120 118 4.5 5.5 5.4 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 supply current, i cc (ma) supply voltage, v cc (v) v io = 5v t a = 25c data rate = 1mbps 09293- 1 14 figure 19 . supply current, i cc vs . supply voltage v cc ?40 85 60 35 10 ?15 receiver output high voltage, v oh (v) temperature (c) v cc = 5v, v io = 5v, i out = ?1.5ma 4.855 4.860 4.865 4.870 4.875 4.880 4.885 4.890 4.895 09293- 1 15 figure 20 . receiver o utput h igh v oltage vs. temperature ?40 85 60 35 10 ?15 receiver output low voltage, v ol (mv) temperature (c) 0 120 100 80 60 40 20 09293- 1 16 figure 21 . receiver outpu t low v oltage vs. temperature
adm3053 rev. 0 | page 12 of 20 test circuits txd v od v canh v canh v oc r l r l 2 2 09293-006 figure 22 . driver voltage measurement c l rxd canh canl v id 09293-007 figure 23 . receiver voltage measurements canh canl txd rxd c l r l 15pf 09293-008 figure 24 . switching characteristics measure ments r l r s 10f 100nf 10f 100nf 10f 100nf 10f 100nf adm3053 t xd rxd isolation barrier gnd1 gnd2 logic side bus side enc ode de c ode de c ode en c ode oscil l a t or re c tifier regul a t or v isoout di g ital isol a tion ic oupler iso p ower dc-to-dc c on v er t er v io v isoin r s canh canl v ref reference voltage receiver can transceiver txd r s rxd v ref gnd2 v cc slope/ standby driver protection v c c 09293-009 figure 25 . supply current measurement test circuit
adm3053 rev. 0 | page 13 of 20 circuit description c an transceiver operatio n a can bus has two states called dominant and recessive. a dominant state is present on the bus when the differential volt age between canh and canl is greater than 0.9 v. a recessive state is present on the bus when the differential voltage between canh and canl is less than 0.5 v. during a dominant bus state , the canh pin is high , and the canl pin is low. during a recessive bus state, both the canh and canl pins are in the high impedance state. pin 18 (r s ) allows two different modes of operation to be selected: high - speed and s lope control. for high - speed operation, the transmitter output transistors are simply switched on an d off as fast as possible. in this mode, no measures are taken to limit the rise and fall slopes. a shielded cable is recommended to avoid em i problems. high - speed mode is selected by connecting p in 1 8 to ground. slope control mode allows the use of an un shielded twisted pair or a parallel pair of wires as bus lines. to reduce em i, the rise and fall slopes should be limited. the rise and fall slopes can be programmed with a resistor connected from p in 18 to ground. the slope is proportional to the current output at p in 1 8. signal isolation the adm 3053 signal isolation is implemented on the logic side of the interface. the part achieves signal isolation by having a digital isolation section and a transceiver section (see figure 1 ). data applied to the txd pin referenced to logic ground (gnd1) are coupled across an isolation barrier to appear at the transceiver section referenced to isolated ground (gnd2). similarly, the single - ended receiver output signal, referenced to isolated ground in the transceiver section, is coupled across the isolation barrier to appear at the r x d pin referenced to logic ground (gnd1). the signal isolation is powered by the v io pin and allows the digital interface to 3.3 v or 5 v logic. power isolation the adm3053 power isolation is implemented using an iso power integrated isolated dc - to - dc converter. the dc - to - dc converter section of the adm 3053 works on principles that are common to most modern power supplies. it is a secondary side controlle r architecture with isolated pulse - width modulation (pwm) feedback. v cc power is supplied to an oscillating circuit that switches current into a chip - scale air core transformer. power transferred to the secondary side is rectified and regulated to 5 v. t h e secondary (v iso ) side controller regulates the output by creating a pwm control signal that is sent to the primary (v cc ) side by a dedicated i coupler data channel. the pwm modulates the oscillator circuit to control the power being sent to the secondary s ide. feedback allows for significantly higher power and efficiency. truth tables the truth tables in this section use the abbreviations found in table 9 . table 9 . truth table abbreviations letter description h high level l low level x dont care z high impedance (off ) i indeterminate nc not connected table 10 . transmitting supply status input outputs v io v cc txd bus state canh canl on on l dominant h l on o n h recessive z z on on floating recessive z z off on x recessive z z on off l indeterminate i i table 11 . receiving supply status inputs output v io v cc v id = canh ? canl bus state rxd on on 0.9 v dominant l on on 0.5 v r ecessive h on on 0.5 v < v id < 0.9 v x 1 i on on inputs open recessive h off on x 1 x 1 i on off x 1 x 1 h 1 x = dont care. thermal shutdown the adm305 3 contain s thermal shutdown circuitry that protects the part from excessive power dissipation during fau lt conditions . shorting the driver outputs to a low impedance source can result in high driver currents. the thermal sensing circuitry detects the increase in die temperature under this condition and disables the driver outputs. this circuitry is designed to disable the driver outputs when a die temperature of 1 5 0c is reached. as the device cools, the drivers are reenabled at a temperature of 1 4 0c . dc correctness and m agnetic field immuni ty the digital signals transmit across the isolation barrier using i coupler te chnology. this technique uses chip - scale transformer windings to couple the digital signals magnetically from one side of the barrier to the other. digital inputs are encoded into waveforms that are capable of exciting the primary transformer
adm3053 rev. 0 | page 14 of 20 win ding. at the secondary winding, the induced waveforms are decoded into the binary value that was originally transmitted. positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer . the decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. in the absence of logic transitions at the input for more than 1 s, periodic sets of refresh pulses indicative of the correct input state a re sent to ensure dc correctness at the output. if the decoder receives no internal pulses of more than approximately 5 s, the input side is assumed to be unpowered or nonfunctional, in which case, the isolator output is forced to a default state by the w atchdog timer circuit. this situation should occur in the adm305 3 devices only during power - up and power - down operations. the limitation on the adm3053 magnetic field immunity is set by the condition in which induced voltage in the transformer receiving c oil is sufficiently large to either falsely set or reset the decoder. the following analysis defines the conditions under which this can occur. the 3.3 v operating condition of the adm 3053 is examined because it represents the most susceptible mode of op eration. the pulses at the transformer output have an amplitude of >1.0 v. the decoder has a sensing threshold of about 0.5 v, thus establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is gi ven by v = (?d / dt )? r n 2; n = 1, 2, , n where: is magnetic flux density (gauss). n is the number of turns in the receiving coil. r n is the radius of the n th turn in the receiving coil (cm). given the geometry of the receiving coil in the adm3053 and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated as shown in figure 26. magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 1m 10 0.01 1k 10k 10m 0.1 1 100m 100k 09293-010 figure 26 . m aximum allowable external magnetic flux density for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does n ot cause a faulty output transition. similarly, if such an event occurs during a transmitted pulse (and is of the worst - case polarity), it reduces the received pulse from >1.0 v to 0.75 v, which is still well above the 0.5 v sensing threshold of the decode r. the preceding magnetic flux density values correspond to specific current magnitudes at given distances from the adm 3053 transformers. figure 27 expresses these allowable current magnitudes as a function of fre quency for selected distances. as shown in figure 27 , the adm 3053 is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. for the 1 mhz examp le, a 0.5 ka current must be placed 5 mm away from the adm 3053 to affect component operation. magnetic field frequency (hz) maximum allowable current (ka) 1k 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 09293-0 1 1 figure 27 . maximum allowable current for various current - to - adm 3053 spacings note that in combinations of strong magnetic field and hig h frequency, any loops formed by the printed circuit board (pcb) traces can induce error voltages sufficiently large to trigger the thresholds of succeeding circuitry. proceed with caution in the layout of such traces to prevent this from occurring .
adm3053 rev. 0 | page 15 of 20 applications information pcb layout the adm3053 signal and power isolated can transceiver contains an iso power integrated dc-to-dc converter, requiring no external interface circuitry for the logic interfaces. power supply bypassing is required at the input and output supply pins (see figure 28). the power supply section of the adm3053 uses a 180 mhz oscillator frequency to pass power efficiently through its chip-scale transformers. in addition, the normal operation of the data section of the i coupler introduces switching transients on the power supply pins. bypass capacitors are required for several operating frequencies. noise suppression requires a low inductance, high frequency capacitor, whereas ripple suppression and proper regulation require a large value capacitor. these capacitors are connected between gnd1 and pin 6 (v io ) for v io . it is recommended that a combination of 100 nf and 10 nf be placed as shown in figure 28 (c6 and c4. it is recommended that a combination of two capacitors are placed between pin 8 (v cc ) and pin 9 (gnd1) for v cc as shown in figure 28 (c2 and c1). the v isoin and v isoout capacitors are connected between pin 11 (gnd2) and pin 12 (v isoout ) with recommended values of 100 nf and 10 f as shown in figure 28 (c5 and c8). two capacitors are recommended to be fitted pin 19 (v isoin ) and pin 20 (gnd2) with values of 100nf and 10nf as shown in figure 28 (c9 and c7). the best practice recommended is to use a very low inductance ceramic capacitor, or its equivalent, for the smaller value. the total lead length between both ends of the capacitor and the input power supply pin should not exceed 10 mm. 09293-012 figure 28. recommended pcb layout in applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. furthermore, design the board layout such that any coupling that does occur equally affects all pins on a given component side. failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings for the device, thereby leading to latch-up and/or permanent damage. the adm3053 dissipates approximately 650 mw of power when fully loaded. because it is not possible to apply a heat sink to an isolation device, the devices primarily depend on heat dissipation into the pcb through the gnd pins. if the devices are used at high ambient temperatures, provide a thermal path from the gnd pins to the pcb ground plane. the board layout in figure 28 shows enlarged pads for pin 1, pin 3, pin 9, pin 10, pin 11, pin 14, pin 16, and pin 20. implement multiple vias from the pad to the ground plane to reduce the temperature inside the chip significantly. the dimensions of the expanded pads are at the discretion of the designer and dependent on the available board space. emi considerations the dc-to-dc converter section of the adm3053 must, of necessity, operate at very high frequency to allow efficient power transfer through the small transformers. this creates high frequency currents that can propagate in circuit board ground and power planes, causing edge and dipole radiation. grounded enclosures are recommended for applications that use these devices. if grounded enclosures are not possible, good rf design practices should be followed in the layout of the pcb. see the an-0971 application note, control of radiated emissions with isopower devices , for more information. insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. analog devices conducts an extensive set of evaluations to determine the lifetime of the insulation structure within the adm3053. accelerated life testing is performed using voltage levels higher than the rated continuous working voltage. acceleration factors for several operating conditions are determined, allowing calculation of the time to failure at the working voltage of interest. the values shown in table 5 summarize the peak voltages for 50 years of service life in several operating conditions. in many cases, the working voltage approved by agency testing is higher than the 50 year service life voltage. operation at working voltages higher than the service life voltage listed leads to premature insulation failure. the insulation lifetime of the adm3053 depends on the voltage waveform type imposed across the isolation barrier. the i coupler insulation structure degrades at different rates, depending on whether the waveform is bipolar ac, unipolar ac, or dc. figure 29, figure 30, and figure 31 illustrate these different isolation voltage waveforms.
adm3053 rev. 0 | page 16 of 20 bipolar ac voltage is the m ost stringent environment. a 50 year operating lifetime under th e bipolar ac condition determines the analog devices recommended maximum working voltage. in the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. this allows operation at higher working volt ages while still achieving a 50 year service life. the working voltages listed in table 5 can be applied while maintaining the 50 ye ar minimum lifetime, provided the voltage conforms to either the unipolar ac or dc voltage cases. any cross insulation vo ltage waveform that does not conform to figure 30 or figure 31 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50 - yea r lifetime voltage value listed in table 5 . 0v rated peak voltage 09293-013 figure 29 . bipolar ac waveform 0v rated peak voltage 09293-014 figure 30 . dc waveform 0v rated peak voltage notes 1. the voltage is shown as sinusodial for illustration purposes only. it is meant to represent any voltage waveform varying between 0 and some limiting value. the limiting value can be positive or negative, but the voltage cannot cross 0v. 09293-015 figure 31 . unipolar ac waveform
adm3053 rev. 0 | page 17 of 20 typical a pplications figure 32 is an example circuit diagram using the adm3053. can controller 3.3v/5v supply 100nf 10nf 100nf 10nf canh canl r t bus connector 5v supply 100nf 10f 10f 100nf r s adm3053 t xd rxd isolation barrier gnd1 gnd2 logic side bus side enc ode de c ode de c ode enc ode oscil l a t or re c tifier regul a t or v isoout di g ital isol a tion ic oupler iso p ower dc-to-dc c on v er t er v io v isoin r s canh canl v ref reference voltage receiver can transceiver txd r s rxd v ref gnd2 v cc slope/ standby driver protection v c c 09293-016 figure 32 . example circuit diagram using the adm3053
adm3053 rev. 0 | page 18 of 20 outline dimensions controlling dimensions are in millimeters; inch dimensions (in p arentheses) are rounded-off millimeter equiv alents for reference onl y and are not appropria te for use in design. compliant t o jedec st andards ms-013-ac 13.00 (0.51 18) 12.60 (0.49 61) 0.30 (0.01 18) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.41 93) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.02 01) 0.31 (0.0122) sea ting plane 8 0 2 0 1 1 1 0 1 1.27 (0.0500) bsc 06-07-2 006- a figure 33 . 20 - lead standard small outline package [soic_w] wide body (rw - 20) dimensions shown in millimeters and (inches) ordering guide model 1 temperature range package description package option adm3053 brwz ?40c to +85c 20- lead soic_w rw -20 adm3053 brwz - reel7 ?40c to +85c 20- lead soic_w rw -20 eval - adm3053ebz adm3053 evaluation b oard 1 z = rohs compliant part.
adm3053 rev. 0 | page 19 of 20 notes
adm3053 rev. 0 | page 20 of 20 notes ? 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09293 - 0 - 5/11(0)

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